Frontemare di Trieste
Istituto Nazionale di Fisica Nucleare
Sezione di Trieste


CASIS2 is a 3-year R&D program that continues the development of very-large dynamic range VLSI front-end electronics for silicon-tungsten calorimeters (especially for space experiments) started with the previous CASIS experiment. The objective of CASIS2 is to integrate within a single chip the analog front-end part and the analog-to-digital conversion part. During 2007 we have designed, produced and tested the prototype chip Casis1.1 (realized in a 0.35 μm CMOS technology by AustriaMicroSystems).

The design of the Casis1.1 chip includes 2 complete front-end channels (double-gain CSA, time variant shaper based on a Correlating Double Sampling structure and output buffer) and 9 ADC channels. This chip included all the "lessons learned" from the analysis and laboratory characterization of the first version (CASIS1.0, which was the arrival point of the previous experiment CASIS).

Concerning the front-end part, only minor modifications and improvements (mainly in the CSA feedback and control networks) were introduced with respect to CASIS1.0, since the results obtained with the first prototype were already fully compliant with the design specifications in terms of noise, dynamic range, linearity and power consumption).

Test results on the Casis1.1 prototype have shown that the random device mismatch problems in the ADC have been entirely solved with the new design.

CASIS2 pictures



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