Frontemare di Trieste
Istituto Nazionale di Fisica Nucleare
Sezione di Trieste

The Electronic Readout

Index

The Hal25 Chip

The Chipcables

The Hybrid

The EndCap

The FEROM Modules

The Hal25 Chip

The HAL25 is a mixed analogue-digital ASIC designed for the SSD read-out. HAL25 has been designed in a 0.25 micron CMOS process; in addition, special design techniques have been used to meet the demands of low noise, low power consumption and radiation hardness required by the ALICE experiment. HAL25 has a very large dynamic range (about ± 350.000 electrons, corresponding to about ± 14 MIPs in the case of 300 µm thick sensor) with a good linearity. The linearity of the response over the total dynamic range is shown in Figure 1 as resulted from laboratory measurements.

Figure 1: HAL25 dynamic range: for signals within the ±14 MIP range, the response is linear, with an error ≤ 4%.

The chip has 128 input channels in a single row with 80 µm pitch and all its functionalities are remote-controlled via JTAG protocol. Each channel consists of a preamplifier, a shaper and a capacitor to store the voltage signal proportional to the collected charge on a strip of the sensor. The pre-amplifier converts the charge input from the sensor into an analogue voltage step whose magnitude is a function of the charge. It uses a signal shaper whose shaping time is adjustable between 1.4 and 2.1 µs. The analogue signals are stored in a sample-hold circuit, controlled by an external HOLD signal. Once the analogue signals are stored they can be read out serially at 10 MHz through an analogue multiplexer. This voltage signal is finally converted to a differential current signal by a differential output buffer. A fast clear input allows abortion of the readout sequence when the event is rejected by the ALICE trigger system. The chip is programmable via the JTAG protocol which allows:

  • to tune the parameters of the analogue chains;
  • to check the analogue behaviour of the chip by injecting adjustable charges to the inputs of selected channels with a programmable pulse generator;
  • to test the interconnections and the chip functionalities (boundary scan).

These tests and read-out operations would be otherwise unfeasible, given the extremely reduced dimensions of its components: the particular technique used to connect the chip to the conducting traces allowed to reduce the channel pitch to 80 µm and the global chip dimensions to 11.9 mm × 3.65 mm × 0.15 mm.

The Chipcables

The chipcables consist of a 10 µm thick polyimide foil which supports 14 µm thick aluminum traces. A chipcable fitting in a plastic frame, which facilitates handling and testing, is shown in Figure 2. All connections between the chips and the sub-hibrid and between the chips and the sensor are made by chip-cables connected via TAB 2 bonding. They allow for an easy testing of the chip before further use and function as a pitch adapter between the sensor pads (95 µm pitch) and the chip input pads (80 µm pitch). In addition, the use of a exible connection between sensor and electronics makes it possible to fold the hybrids on top of the sensor, creating a compact object.

Figure 2: A framed microcable assembled with the chip to form a framed-chip. Once the microcable traces have been aligned with the pads of the chip, they are connected via TAB technique. Only the microcable region within the dashed red line is actually assembled in the detector, while the rest has the only functions to contact the test system and to t in the plastic frames. Once connected to the HAL25 chip and tested, the surplus part is cut away.

The Hybrid

The hybrid is obtained placing six HAL25 chips on a sub-hybrid, i.e. an aluminum-on-polyimide hybrid circuit supported by a carbon fi bre stiffener. The sub-hybrid is shown in Figure 3.

Figure 3: A hybrid, with 6 chips bonded on top. The carbon fi ber stiffener is on the rear side.

The sub-hybrid is made of a two layer flex circuit, each layer having 30 m thick aluminum traces on top of 20 m polyimide. It hosts power lines as well as digital and analog lines needed for controlling and reading the chips, while the stiffener provides mechanical support and cooling distribution. The electrical connections between the chip channels and the sensor strips are obtained bonding the aluminum chipcable traces with the pads present on the sensor surface via tape automatic bonding (TAB) technique (128 connections per chip); the same for the connections between chip and sub-hybrids traces (~55 connections per chip). This assembly provides optimal electrical, mechanical and thermal performances associated to a very low mass for good radiation transparency.

The EndCap

The EndCap is the interface for and distributor of the control and data signals between the detector modules and the data acquisition, placed at a distance of 25 m away. Each EndCap module is composed out of (see Figure 4): - 1 Interface-Card, which interfaces the module hybrids with the read-out FEROM;

  • 1 to 7 SupplyCards (usually 7), each connected to 2 module hybrids; they manage the analogue signals and their transfer to the FEROM; in addition, they provide a measurement of the bias current and the temperature of the modules;
  • a BasePlate or PCB, which hosts and connects together the other EndCap components;
  • a CableCard which has all cables for the connections to the data acquisition and the control system.

Figure 4: The EndCap modules. The main components are indicated in the scheme, hosted by the PCB backplane: the Interface between front-end hybrids and read-out modules, the Supply Cards managing the analogue signals and measuring the bias current and the temperature of the modules, the Cable Card connecting the EndCap with the data acquisition and the control system.

The EndCap tasks can be summarized into four main functions:

  • Power control and protection.
    The power supplies for the detectors, for the EndCap ground level electronics and the bias level electronics are all floating supplies with sense wires up to the EndCap. The connections between the experiment ground and the floating grounds, like P-side ground and N-Side ground are made inside the EndCap. The mechanics is at experiment ground level, and forms a shield around each EndCap. In this way the analogue buffer is very close to the signals source and ground reference, and it is shielded. This approach should prevent electromagnetic interference. Taking into account the ALICE environment, the EndCap electronics are protected against malfunctions deriving from the expected 50krad total ionizing dose expected during the experiment life time. Radiation tolerant design techniques allow the devices to survive Single Event Eects (SEE), i.e. damages in the electroncis caused by single ionizing particles, and to avoid any Single Event Upset (SEU), i.e. a change of state caused in a register by ions or electro-magnetic radiation.
  • Signal buffering and coupling.
    The analogue signals from the front-end are buffered. For the readout of the two detector sides an analogue multiplexer is required. These two functions are integrated in an integrated circuit, the ALABUF. Since the double-sided detectors use front-end read-out electronics operating at dierent potentials for the dierent sides, all signals are AC coupled to the corresponding voltage level to avoid the data acquisition and control electronics to operate at the front-end bias potentials.
  • Readout Control.
    The HAL25 serial read-out mechanism allows the ECM to have one analog output for each SSD-module, which consists of 1536 signals, one for each strip. The ECM also has an error output signal to indicate token errors and power supply problems. To start the readout, the front-end chip requires a token and a clock signal. These signals are distributed by the ALCAPONE chips, which also controls the token delay and the analogue multiplexer, the power supply control, the status monitoring and the error handling.
  • JTAG detector control and monitoring.
    The front-end electronics is controlled via the serial JTAG bus. This bus is also used to monitor and control the EndCap functions: errors like latch-up and high detector current can be monitored, and appropriate action can then be taken; through the JTAG protocol, moreover, disabled or broken front-end chips, hybrids and EndCap PCB's can be bypassed and this information is available for the data acquisition system.

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The FEROM modules

The read-out signals are sent by the EndCaps to the FEROM system, located in the cavern just outside the ALICE magnet. The FEROM is in charge for the digitization of the signals from each of the SSD 1698 detection modules in parallel, namely 2.6 million analogue samples per event at the trigger rate of ALICE. It is also connected to the data acquisition system, the detector control system and the central trigger processor. An overview of the SSD read-out system is schematically shown in Figure 5.

Figure 5: The SSD read-out scheme. Notice that the double-sided detectors and their electronics operate at floating voltage levels: the AC coupling connections between the real ground and local module P-side and N-side "grounds" are performed by the EndCaps. The Endcap interfaces with the FEROM providing the read-out, the control and the trigger.

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