The two layers of the SSD contain a total of 1698 modules. In additions, the construction of spare devices is requested: therefore the overall number of produced SSD modules grows up to about 2000. These large numbers require an efficient assembly procedure and an exhaustive test protocol. The procedures have been designed and scheduled in order to allow the monitoring of the operations: at the end of each single production stage the intermediate products have been tested in order to verify their complete functionalities, both with electronic tests and with accurate visual inspections. The module assembly is split in three steps:
- In the first step HAL25 front-end chip is assembled with a chipcable into a tabbed chip: the chipcable pads and the chip pads are aligned to match with a precision better than 5 m. Vacuum and mechanical locks keep steadily in position the chip and the chipcable through specically designed holders. The pads are connected via TAB bonding and the product (the so called tabbed-chip) is tested; after disposing a protective glue on the bonds, the tabbed-chips are tested again and cut out from the frame. The procedure is summarized in Figure. 1;
Figure 1: The assembly steps of a chip on the microcables. From top: the chipcable fitting a frame is aligned and bonded with a chip; the assembled tabbed-chip is glued to protect the bonds and tested
- Six tabbed-chips are then mounted on a sub-hybrid to make a hybrid: the procedure uses a hybrid holder equipped with seven separate vacuum lines to keep a sub-hybrid and six tabbed-chips in position. In the hybrid building phase the hybrid holder is placed on the aligning base, where also sits a dummy sensor. Once the tabbed chips are aligned with the sub-hybrid and with the dummy sensor pads at the same time, the chips are glued on the sub-hybrids; finally they are interconnected via TAB bonding to form a hybrid, that is then tested. Figure 2 schematically shows the operations performed in this step;
Figure 2: The assembly steps of a framed chip on a hybrid. From top: six working framed chips are cut out from the frame and connected via TAB bonding to a sub-hybrid forming a hybrid; the bondings are then protected and fixed with glue; thus the hybrid is tested.
- Finally, two hybrids are mounted on a sensor according to the schemes of Figure 3: firstly a hybrid is aligned on the sensor and its traces are TAB-bonded on the sensor pads; the resulting half-module is accurately tested. Then the half-module is flipped up side down and the second hybrid is aligned and interconnected. The produced module is tested and its hybrids are folded on top of the sensor. The module is now ready for the final quality validation test.Figure 3: The three assembly steps of two hybrids on a sensor. From top: the hybrids are aligned and bonded on the module in two steps as by the figure. The device is tested after each operation; both hybrids are folded on one side of the produced module.
The strict requirements imposed to the SSD performances by the ALICE physics programme forced to keep the quality of the modules close to the full efficiency. In order to provide the required spatial resolution and to measure the specific ionization with an acceptable signal-to-noise ratio over the full azimuthal coverage and over the two central units of pseudorapidity, the quality of the components before and after each single assembly operation was evaluated and monitored: the goal was to produce devices with at least 98% properly working channels out of the 1536 channels of a module. A complex and at the same time very general test was designed to help achieve this challenging objective: such a test is expected both to completely characterize each single SSD channel and to measure the global properties of the produced devices; in addition, it should be comprehensive enough to spot and identify also unexpected and exotic defects, possibly suggesting their origin. The test applied during the construction operations is based on the measurement of some basic parameters and on the processing of the acquired data, which results in a quite fine defect identification. In the following paragraphs the parameters which have been the object of the tests are described in detail and the procedure is explained. In addition the specific tests that have been carried out in case of particular problems and defects are presented.
Measuring a set of simple parameters, the test system is capable to evaluate the general behaviour and the single channel functionalities of an SSD module; through the interpretation of these measurements, it identifies eventual construction defects. The stages of the test procedure are described hereafter.
- The digital tests and settings.
A first phase of the test is devoted to check the JTAG registers, the connection chain and the internal components of the chips. In this phase, the chips are recognized and their serial number is read-out; the voltage and current parameters of the chip are set at the desired values; the analogue read-out is enabled.
- Single channels response.
The output response of each channel is evaluated for the unbiased sensor. Through a sample of acquisitions triggered at a fixed frequency, the test system evaluates for each channel the characteristic offset (fig. 4), i.e. the pedestal, and noise (fig. 5), as the mean and the variance of the signal distribution; this distribution is typically Gaussian, as veried on a large sub-sample of channels. The coherent oscillations of the baseline of groups of adjacent channels, the so called common mode noise, is calculated as well by the test software, and corrected; for a detailed description of the algorithm used to calculate noise, pedestal and common mode. Afterwards, injecting an adjustable charge quantity into the channel input through the internal HAL25 pulser, the test system measures the output response (fig. 6). These measurements, which are repeated also while applying the bias voltage, will be later used to identify possible defects.
Figure 4: The pedestal of the P-side (left) and N-side (right) channels.
Figure 5: Noise measurement without applying any bias voltage. The noise is shown as a function of the P-side (left) and N-side (right) channel number.
Figure 6: Undepleted sensor response to a charge injected in the channel inputs by the HAL25 internal pulser. On the P-side (left plot) one channel with zero-response is visible close to channel 512.
- The I-V curve.
The leakage current is measured as a function of the applied bias voltage, both polarizing the sensor in reverse bias for defining the depletion voltage, and in direct bias, to spot eventual problems in the bias circuits of the electronics and of the sensor. The depletion voltage is defined observing the behaviour of the N-side noise as a function of the increasing applied bias voltage: the value where the noise reaches the stability is taken as the depletion voltage.
- Defect identication.
The resulting depletion voltage is applied to the sensor. The response of the channels is evaluated without (fig. 7) and with (fig. 8) injected signals at the inputs and the results are cross checked to detect and classify the defects in the following categories:
- Dead channels: the channels presenting very low response (< 10% of the mean response of the module side) to injected charges, and with low noise (< 50% of the mean noise of the module side) are tagged as dead; these effect are probably caused by broken components in the signal processing chain.
- Open channels: the connection between the sensor and the electronics is interrupted somewhere; when no bias voltage is applied, this results in a lower noise with respect to the mean noise level, since the contribution to the noise of the input load capacitance is absent for such channels; moreover they present an enhanced response to the charge injection since no charge is lost in the sensor, which is disconnected in this case.
- Noisy channels: the channels are tagged as noisy if they have measured noise larger than a fixed threshold defined on the basis of the required signal-to-noise ratio.
- Low-gain channels: some channels present a response to an injected charge different from the behaviour of the rest of the module side; the preamplifying electronics of the channels with such a problematic gain is not properly working.
- Broken AC: a damage in the silicon-oxide-metal system can cause a modification in the capacitive network of a channel, e.g. shorting the aluminum pad to the underneath implant. This defect weighs on the noise measured in direct and reverse bias and on the response: it is spotted by the test system taking into account all these measured effects.
- Short-circuited channels: the internal pulser injects a charge in one input at a time and the neighbouring channels is read-out; if a not negligible response is recorded, the channels are tagged as shorted.
Figure 7: The noise measured at the depletion voltage. The peaks show the presence of high noise channels both on P-side (left) and N-side (right).
Figure 8: The response to the injected charge at the depletion voltage is measured; through a system of thresholds (coloured dashed lines in the plot) the functionalities of the pre-amplifying electronics is evaluated. The P-side channel with zero-response, already detected without applying any bias voltage, is visible on the left panel.
- Global quality assessment.
The overall quality of the detector has to be univocally and homogeneously defined, regardless of the different types of defects, in order to allow a direct comparison with a quality standard or between different modules. The quality mark is obtained counting the single channel defects and subtracting this computed number from 100: a module without defects has quality Q = 100; the maximum acceptable number of defects is equal to the 2% of the total amount of channels, i.e. 30 channels out of 1536, that corresponds to a minimum required quality of Q=(100-30)=70. In presence of serious global defects like high bias current or an interruption in the digital chain, the assessed quality is Q=0.
- Transparent test.
At the end of the test procedure, in order to monitor the shape of the output signals, the first defect-free channel is considered: its response to an injected pulse is sampled and plotted as a function of the time. The final output of the test system is showed by the screenshot in fig. 9 in the case of 100% quality module, i.e. in absence of defects. The results of the measurements and the defects are also saved in a textual report and stored in an on-line database.
Figure 9: Screenshot of the test system output showing the test results for a good quality object, i.e. a module with more than 98% properly working channels. The plots show on two columns corresponding to the p-side (left) and the n-side (right) the results of the measurements of the following quantities as a function of the channel number: the noise before the depletion (1), the response to an injected pulse signal before the depletion (2), the noise after the depletion (3), the pedestal (4), the response after the depletion (5), the computed parameter used for the denition of the broken ACs (6) and the shorted channels (7). On the right section of the screenshot, a summary of the defects, divided by defect class, is presented; moreover, the digital test results (8), the depletion and breakdown voltages are shown. The last bottom right plot (9 ) shows the typical shape of a read-out. The global quality is finally computed and shown.
The detection of the defects, which was performed simultaneously with the assembly operations, allowed to give a feedback to the production, resulting in a continuous tuning of the bonding parameters, in the choice of the most suitable materials and tools for the different operations and in the improvement of the procedures. In this way, a large number of defect typologies was solved during the mass production and mainly regarded very localized problems. For a complete list and description of the defect and problems faced during the production phase see the Giacomo's Contin PhD Thesis.