Timing information for the SVT Hit Buffer

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The Hit Buffer timing is very delicate.
All clock traces have exactely the same lenght, so all clocks to all chips are synchronous and the same as on test points, other then for adjustments done using roboclock jumpers.
At present the board is now to work at 20 MHz at room temperature with some carefull adjustment of clock edges via the roboclock jumpers (see the jumpers page ). There is some evidence that with the same jumpers the board will run up to 24/25 MHz in the FNAL cooled crate. Clocks at 22 and 23 MHx have been procured and will tested as well. The HB working clock will be adjusted as high as reasonable.

BEWARE Since clock edges had to be moved with the roboclock jumpers, the CLOCK test points on the bottom right of the baord do not aling anymore with the reference quartz.
The phases among the 3 test points, when using a 20Mhz quarts and jumpers settings as currently reccomanded is described in the jumpers page ). That settings is made to achieve (in cypress terminology):

U64:  no change
U65: 4F0 high         ==> +2 Tu on Out4 = CLK1/2   to OUTn  chips
U66: 4F1 low 4F0 high ==> -4 Tu on Out4 = DNCLK3/4 to ENMAP chip
U67:   no change

The phase relationship between the CLK testpoint and the closest edge of each HB clock, measured on the roboclock pins, is listed here as measured on a working Hit Buffer board, notice that is very difficutl to resolve less then 0.5 nsec on the scope. This is meant to be used to check that all roboclocks are working in case of doubt.

CLK1:  -4.3 ns
CLK2:  -4.1 ns
CLK3:  -7.7 ns
CLK4:  -7.7 ns
CLK5:  -7.7 ns
CLK6:  -7.7 ns
CLK7:  -7.7 ns
CLK8:  -7.7 ns
CLK9:  -7.4 ns
CLK10: -7.5 ns

NCLK1: -7.4 ns
NCLK2: -6.9 ns
NCLK3: -6.9 ns
NCLK4: -6.9 ns
NCLK5: -6.8 ns
NCLK6: -6.8 ns

DCLK:  -7.6 ns
DCLK2: -7.6 ns
DCLK3: -7.5 ns
DCLK4: -7.5 ns

DNCLK:   -7.4 ns
DNCLK2:  -7.4 ns
DNCLK3: -10.3 ns
DNCLK4: -10.3 ns
DNCLK5:  -7.2 ns
DNCLK6:  -7.2 ns
DNCLK7:  -6.9 ns
DNCLK8:  -6.9 ns
DNCLK9:  -6.9 ns
DNCLK10: -6.9 ns

Stefano Belforte