--*********************************************************************** -- GLUE3: AMS GLUE -- -- |*******************************************************************| -- | NOTA BENE: THROUGHOUT THE CODE THE LOWERCASE "n" SUFFIX DENOTATES | -- | A LOW ACTIVE SIGNAL. OTHERWISE ALL SIGNALS ARE HIGH ACTIVE. | -- |*******************************************************************| -- -- Inside the design ALL SIGNALS ARE HIGH ACTIVE (i.e. only pins are in -- negative logic). -- -- VHDL binding architecture by E.Meschi - July 1996 -- for Cypress pASICs -- -- Use package toppkg3 (top level modules) -- Address bus is 16 bits (UP) and 14 bits (DW) -- Always in PIPE mode -- VME data_valid implemented -- Adds TopFsm to dialogue with AMS -- UpFsm is in RESET status whenever OPC is /= output -- -- DownFsm is in Reset whenever no valid data is present on inputs -- (DV_IN = '0') -- -- EM / SB : 20-01-1997 -- Rev.2.0 -- TOPFSM3 Added, address register has one more pipeline stage -- Data valid is registered within TOPFSM3 -- -- SB 07-03-1997 -- modified for WARP v 2.4 running on SUN (add pad_gen, remove most packages) -- -- SB 11-03-1997 -- change pin assignements to agree with AMS PCB layout -- -- SB 25-03-1997 -- rename _TOP the signals for/from TOP FSM also in pins, add comments, -- improve readibility, re-organize FSM's -- -- SB 03-04-1997 -- use Warp options to handle fanout limits -- -- SB 29-06-1997 -- use AMSGLUE.CTL control file to assing flip-flops close to -- output pins for all registered output signals -- Synchronize DV_DOWN_ before making logic for down FSM -- -- SB 15-07-1997 -- move all attributes to AMSGLUE.CTL file -- --*********************************************************************** -- top level entity/architecture is GLUE3 use work.toppkg3.all; Entity Glue3 is port( CLK1: in BIT; DATA_UP: in BIT_VECTOR (11 downto 0); DATA_DW: out BIT_VECTOR (11 downto 0); LAYER_UP: in BIT_VECTOR (2 downto 0); LAYER_DW: out BIT_VECTOR (2 downto 0); OPCODE_UP: in BIT_VECTOR (3 downto 0); OPCODE_DW: out BIT_VECTOR (3 downto 0); ADDRESS_UP: inout BIT_VECTOR (15 downto 0); ADDRESS_DW: in BIT_VECTOR (13 downto 0); SEL_TOPn: in BIT; SEL_DWn: out BIT_VECTOR (3 downto 0); DONE_TOPn: in BIT; DONE_DWn: out BIT; DV_TOPn: out BIT; DV_DWn: in BIT_VECTOR (3 downto 0); TMODE: in BIT; VME_DV: in BIT ); attribute pin_numbers of glue3:entity is "ADDRESS_DW(0):82 " & "ADDRESS_DW(1):81 " & "ADDRESS_DW(2):80 " & "ADDRESS_DW(3):79 " & "ADDRESS_DW(4):78 " & "ADDRESS_DW(5):77 " & "ADDRESS_DW(6):76 " & "ADDRESS_DW(7):75 " & "ADDRESS_DW(8):74 " & "ADDRESS_DW(9):73 " & "ADDRESS_DW(10):72 " & "ADDRESS_DW(11):71 " & "ADDRESS_DW(12):70 " & "ADDRESS_DW(13):69 " & "ADDRESS_UP(0):45 " & "ADDRESS_UP(1):44 " & "ADDRESS_UP(2):43 " & "ADDRESS_UP(3):41 " & "ADDRESS_UP(4):40 " & "ADDRESS_UP(5):39 " & "ADDRESS_UP(6):37 " & "ADDRESS_UP(7):36 " & "ADDRESS_UP(8):34 " & "ADDRESS_UP(9):33 " & "ADDRESS_UP(10):32 " & "ADDRESS_UP(11):31 " & "ADDRESS_UP(12):30 " & "ADDRESS_UP(13):29 " & "ADDRESS_UP(14):28 " & "ADDRESS_UP(15):27 " & "CLK1:12 " & "DATA_DW(0):97 " & "DATA_DW(1):96 " & "DATA_DW(2):95 " & "DATA_DW(3):94 " & "DATA_DW(4):93 " & "DATA_DW(5):91 " & "DATA_DW(6):90 " & "DATA_DW(7):89 " & "DATA_DW(8):87 " & "DATA_DW(9):86 " & "DATA_DW(10):84 " & "DATA_DW(11):83 " & "DATA_UP(0):23 " & "DATA_UP(1):22 " & "DATA_UP(2):21 " & "DATA_UP(3):20 " & "DATA_UP(4):19 " & "DATA_UP(5):18 " & "DATA_UP(6):17 " & "DATA_UP(7):10 " & "DATA_UP(8):8 " & "DATA_UP(9):7 " & "DATA_UP(10):6 " & "DATA_UP(11):5 " & "DONE_TOPn:14 " & "DONE_DWn:46 " & "DV_DWn(0):54 " & "DV_DWn(1):53 " & "DV_DWn(2):52 " & "DV_DWn(3):51 " & "DV_TOPn:100 " & "LAYER_DW(0):68 " & "LAYER_DW(1):67 " & "LAYER_DW(2):60 " & "LAYER_UP(0):26 " & "LAYER_UP(1):25 " & "LAYER_UP(2):24 " & "OPCODE_DW(0):58 " & "OPCODE_DW(1):57 " & "OPCODE_DW(2):56 " & "OPCODE_DW(3):55 " & "OPCODE_UP(0):4 " & "OPCODE_UP(1):3 " & "OPCODE_UP(2):2 " & "OPCODE_UP(3):1 " & "SEL_DWn(0):50 " & "SEL_DWn(1):49 " & "SEL_DWn(2):48 " & "SEL_DWn(3):47 " & "SEL_TOPn:15 " & "TMODE:98 " & "VME_DV:99 "; --attribute pad_gen of CLK1:signal is pad_clock; --attribute pad_gen of SEL_TOPn:signal is pad_hd1; end glue3; ------------------------------------------------------------------------ Architecture ArchGlue3 of Glue3 is -- internal high active signals: signal DONE_TOP: BIT; signal DV_TOP: BIT; signal DONE_DW: BIT; signal DV_DW: BIT_VECTOR (3 downto 0); signal SEL_DW: BIT_VECTOR (3 downto 0); signal SEL_UP: BIT; --attribute max_load of DONE_DW:signal is 1; --attribute buffer_gen of DONE_DW:signal is buf_register; begin DONE_TOP <= not DONE_TOPn; DV_TOPn <= not DV_TOP; DONE_DWn <= not DONE_DW; SEL_UP <= not SEL_TOPn; -- note that TOP FSM does not use SEL_, so -- the top level SEL_ is fed directely to -- UP FSM in the positive logic SEL_UP negate: process (DV_DWn, SEL_DW) begin for i in 3 downto 0 loop DV_DW(i) <= not DV_DWn(i); SEL_DWn(i) <= not SEL_DW(i); end loop; end process negate; -- internal logic u1: InDataCell3 port map (CLK1, DATA_UP, DATA_DW); u2: InLayerCell3 port map (CLK1, LAYER_UP, LAYER_DW); u3: InOpcodeCell3 port map (CLK1, OPCODE_UP, OPCODE_DW); u4: OutputEngine3 port map (CLK1, ADDRESS_UP, SEL_UP, DONE_TOP, DV_TOP, OPCODE_UP, ADDRESS_DW, DV_DW, TMODE, VME_DV, SEL_DW, DONE_DW); end ArchGlue3;