/*************************************************************************/
/*                OGLULE_SPECIALS                                        */
/* special functions that need to be instantiated in SYNOPSIS but        */
/* should be omitted from the verilog used for simulation                */
/*                                                                       */
/*                                                                       */
/*************************************************************************/
module oglue_specials (CLK, CLK2);
   input       CLK;
   output      CLK2;
/* wire        ICLK2;
   wire        CLK1;  */
   
/* CLK2 is obtained by CLK dividing the frequency by a factor 8 
   the DIVIDE_BY factor attribute is set on the ck_div.xnf saved in the
   projetc area where XMAKE usually runs as described in the XSI
   release document at page 5-4 */

   CK_DIV  LFclkgen  (.C(CLK), .OSC1(CLK1), .OSC2(ICLK2));
   BUFG_F  LFclkbuf  (.O(CLK2), .I(ICLK2) ); 

 BSCAN boundary_scan ( .TDO(tdo),
		.DRCK(drck),
		.IDLE(idle),
		.SEL1(sel1),
		.SEL2(sel2),
		.TDI(tdi),
		.TMS(tms),
		.TCK(tck),
		.TDO1(tdo1),
  		.TDO2(tdo2)  );

 OBUF bdatao   (.O(otdo), .I(tdo));
 TDO  datao    (.O(otdo));
 IBUF bdatai   (.O(tdi), .I(itdi));
 TDI datai     (.I(itdi));
 IBUF bclocki  (.O(tck), .I(itck));
 TCK clocki    (.I(itck));
 IBUF bmode_sel(.O(tms), .I(itms)); 
 TMS mode_sel(.I(itms));
 
endmodule