/*************************************************************************/
/*                OGLULE_SPECIALS                                        */
/* special functions that need to be instantiated in SYNOPSIS but        */
/* should be omitted from the verilog used for simulation                */
/*     ************ SIMULATION VERSION *********************             */
/*                                                                       */
/*************************************************************************/
module oglue_specials (CLK, CLK2);
  input      CLK;
  output     CLK2;

//
//=================================
//
//  clock_div CK_DIV (CLK, CLK2);

endmodule
//
//=========================================================================
//
module clock_div (CLOCK_IN, CLOCK_OUT);

  input  CLOCK_IN;
  output CLOCK_OUT;
  reg    CLOCK_OUT;

//
  integer nc;
  integer divider;
//
  initial
    begin
      divider = 8;
      nc = 0;
      CLOCK_OUT = 0;
    end
    
  always @ (posedge CLOCK_IN)
    begin
      nc = nc +1;
      if (nc == divider/2+1)
	begin
	  CLOCK_OUT = !CLOCK_OUT;
	  nc = 1;
	end
    end
  
endmodule