/*************************************************************************/
/*                       OGLUE_FSM                                       */
/* Finite State Machine for the Output GLUE's for the AMFPGA chip        */
/* Handles DV/GO protocol and controls the ADDUP register,               */
/* this state machines is common to all glue's but the 0 (talks to       */
/* AMFPGA) and the topmost (talks to AMS), and is independent of the bus */
/* size.                                                                 */
/*                                                                       */
/* 13 Aug 97 S.Belforte: original creation from glue2x10_verbose         */
/*  2 Sep 97 S.Belforte: remove OVERFLOW state and OVERFLOW register     */
/*                       handling, two only states and move one word     */
/*                       each two clock cycles, fully handshacked        */
/*                                                                       */
/*************************************************************************/


`timescale 1ns/1ns

module oglue_fsm (CLK, RESET, SEL, DVDW, GOUP,
                  DVUP, GODW_0, GODW_1, CE_UP);

  input        CLK;
  input        RESET;
  input        DVDW;
  input        GOUP;
  input        SEL;
  output       DVUP;
  output       GODW_0;
  output       GODW_1;
  output       CE_UP;

  reg          DVUP;
  reg          GODW_0,GODW_1;
//
// local nets
//
  reg    [2:0] STATE;
  reg          GODW;
  
//
// enforce one-hot encoding of state register
//
  parameter empty    = 2'b01;
  parameter full     = 2'b10;
//
//-------------------------------------------------
//
// fsm
//
    always @ (posedge CLK)
      begin #1
	DVUP   = 0;
	GODW   = 0;
      	if (RESET) STATE = empty;
      	else
	begin
// state diagram
        case (STATE)
	  empty:   begin
	             if (DVDW) begin
		       STATE = full;
		       GODW  = 1;
		       DVUP  = 1;
		       end
		     else begin
		       STATE = empty;
		       end
	           end
	  full:  begin
		     if (GOUP) begin
		       STATE = empty;
		       end
	             else  begin
		       STATE = full;
		       DVUP = 1;
		       end
	           end
        endcase
        end

        GODW_0 = GODW && !SEL;
        GODW_1 = GODW &&  SEL;

      end                            // end of clock registered part
      
    assign CE_UP  = (STATE == empty)  && DVDW ;

  endmodule