/*************************************************************************/ /* OGLUE */ /* Output GLUE for the AMFPGA chip. This chip works at the lowest glue */ /* level and talks directely to the AMFPGA chips with the OR/SEL protocol*/ /* and slower (divided by 2 or more) clock. The OUT side of this glue */ /* talks the DV/GO protocol to higher level glue's or the AMS board. */ /* Input is from 8 AMFPGA address buses 10-bit each, each bus is common */ /* to two AMFPGA chains (TOP and BOTTOM located respectively on top and */ /* bottom side of the pcb board) correspondong to two different OR/SEL */ /* pair, for a total of 16 incoming 10-bit addresses and thus there is */ /* one 14-bit output address bus. */ /* */ /* 1 Sep 97 S.Belforte: original creation from Paola's GLUE */ /* */ /* */ /* */ /*************************************************************************/ `timescale 1ns/1ns module oglue_sim (CLK, RESET, ORT, ORB, SELT, SELB, ADD0_IN, ADD1_IN, ADD2_IN, ADD3_IN, ADD4_IN, ADD5_IN, ADD6_IN, ADD7_IN, ADD_OUT, DV_OUT, GO_OUT); input CLK; // fast clock input RESET; // global syncrhonous reset input [7:0] ORT; // Output Ready from TOP side AMfpga's input [7:0] ORB; // Output Ready from BOTTOM side AMfpga's output [7:0] SELT; // SELect to TOP side AMfpga's output [7:0] SELB; // SELect to BOTTOM side AMfpga's input [9:0] ADD0_IN; // Adddress busses from AMfpga chains input [9:0] ADD1_IN; input [9:0] ADD2_IN; input [9:0] ADD3_IN; input [9:0] ADD4_IN; input [9:0] ADD5_IN; input [9:0] ADD6_IN; input [9:0] ADD7_IN; input GO_OUT; // GO from higher level GLUE output DV_OUT; // DV to higher level GLUE output [13:0] ADD_OUT; // Address bus to higher level GLUE pulldown (ORT[0]); pulldown (ORT[1]); pulldown (ORT[2]); pulldown (ORT[3]); pulldown (ORT[4]); pulldown (ORT[5]); pulldown (ORT[6]); pulldown (ORT[7]); pulldown (ORB[0]); pulldown (ORB[1]); pulldown (ORB[2]); pulldown (ORB[3]); pulldown (ORB[4]); pulldown (ORB[5]); pulldown (ORB[6]); pulldown (ORB[7]); // //------------------------------------------------- // local nets // wire CLK2; // CLK divided by n wire [10:0] ADD0_0; // Address bus from Level_0 GLUEs wire [10:0] ADD0_1; wire [10:0] ADD0_2; wire [10:0] ADD0_3; wire [10:0] ADD0_4; wire [10:0] ADD0_5; wire [10:0] ADD0_6; wire [10:0] ADD0_7; wire GO0_0, DV0_0; // DV/GO between Level_0 and Level_1 wire GO0_1, DV0_1; wire GO0_2, DV0_2; wire GO0_3, DV0_3; wire GO0_4, DV0_4; wire GO0_5, DV0_5; wire GO0_6, DV0_6; wire GO0_7, DV0_7; wire [11:0] ADD1_0; // Address bus from Level_1 GLUEs wire [11:0] ADD1_1; wire [11:0] ADD1_2; wire [11:0] ADD1_3; wire GO1_0, DV1_0; // DV/GO between Level_1 and Level_2 wire GO1_1, DV1_1; wire GO1_2, DV1_2; wire GO1_3, DV1_3; wire [12:0] ADD2_0; // Address bus from Level_2 GLUEs wire [12:0] ADD2_1; wire GO2_0, DV2_0; // DV/GO between Level_2 and Level_3 wire GO2_1, DV2_1; wire [13:0] ADD3_0; // Address bus from Level_3 GLUEs wire GO3_0, DV3_0; // DV/GO between Level_3 and output // //======================================================= // Executable code // // I/O ports association // assign DV_OUT = DV3_0; assign GO3_0 = GO_OUT; assign ADD_OUT = ADD3_0; // //------------------------------------------------- // // // LEVEL_0 GLUE instantiation: these talks to AMFPga chips, read 10-bit // addresses and output 11-bit addresses. There are 8 of them // clock_div CK_DIV (CLK, CLK2); gl0_2x10 glue0_0 (CLK2, RESET, ADD0_IN, ORT[0], ORB[0], SELT[0], SELB[0], ADD0_0, DV0_0, GO0_0); gl0_2x10 glue0_1 (CLK2, RESET, ADD1_IN, ORT[1], ORB[1], SELT[1], SELB[1], ADD0_1, DV0_1, GO0_1); gl0_2x10 glue0_2 (CLK2, RESET, ADD2_IN, ORT[2], ORB[2], SELT[2], SELB[2], ADD0_2, DV0_2, GO0_2); gl0_2x10 glue0_3 (CLK2, RESET, ADD3_IN, ORT[3], ORB[3], SELT[3], SELB[3], ADD0_3, DV0_3, GO0_3); gl0_2x10 glue0_4 (CLK2, RESET, ADD4_IN, ORT[4], ORB[4], SELT[4], SELB[4], ADD0_4, DV0_4, GO0_4); gl0_2x10 glue0_5 (CLK2, RESET, ADD5_IN, ORT[5], ORB[5], SELT[5], SELB[5], ADD0_5, DV0_5, GO0_5); gl0_2x10 glue0_6 (CLK2, RESET, ADD6_IN, ORT[6], ORB[6], SELT[6], SELB[6], ADD0_6, DV0_6, GO0_6); gl0_2x10 glue0_7 (CLK2, RESET, ADD7_IN, ORT[7], ORB[7], SELT[7], SELB[7], ADD0_7, DV0_7, GO0_7); // // LEVEL_1 GLUE instantiation: condense from 11-bit to 12-bit addresses. // There are 4 of these. // glue2x11 glue1_0 (CLK, RESET, ADD0_0, ADD0_1, DV0_0, DV0_1, GO0_0, GO0_1, ADD1_0, DV1_0, GO1_0); glue2x11 glue1_1 (CLK, RESET, ADD0_2, ADD0_3, DV0_2, DV0_3, GO0_2, GO0_3, ADD1_1, DV1_1, GO1_1); glue2x11 glue1_2 (CLK, RESET, ADD0_4, ADD0_5, DV0_4, DV0_5, GO0_4, GO0_5, ADD1_2, DV1_2, GO1_2); glue2x11 glue1_3 (CLK, RESET, ADD0_6, ADD0_7, DV0_6, DV0_7, GO0_6, GO0_7, ADD1_3, DV1_3, GO1_3); // // LEVEL_2 GLUE instantiation: condense from 12-bit to 13-bit addresses. // There are 2 of these. // glue2x12 glue2_0 (CLK, RESET, ADD1_0, ADD1_1, DV1_0, DV1_1, GO1_0, GO1_1, ADD2_0, DV2_0, GO2_0); glue2x12 glue2_1 (CLK, RESET, ADD1_2, ADD1_3, DV1_2, DV1_3, GO1_2, GO1_3, ADD2_1, DV2_1, GO2_1); // // LEVEL_3 GLUE instantiation: condense from 13-bit to 14-bit addresses. // There is just 1 of these. // glue2x13 glue3_0 (CLK, RESET, ADD2_0, ADD2_1, DV2_0, DV2_1, GO2_0, GO2_1, ADD3_0, DV3_0, GO3_0); endmodule //============================================================================= //============================================================================= `include "gl0_2x10.v" `include "glue2x11.v" `include "glue2x12.v" `include "glue2x13.v" `include "oglue_fsm.v" `include "oglue_specials.v" //============================================================================= //=============================================================================