/*************************************************************************/
/*                GLUE2x11                                               */
/*                                                                       */
/* 2-in 1-out 11-bit GLUE  for the AMFPGA output glue chip (OGLUE)       */
/*  combines two 11-bit input addresses into one 12 bit output according */
/*  to the DV/GO synchronous protocol:                                   */
/*          DV  tells higher glue that data are ready                    */
/*          GO  higher glue signals that it read current data            */
/*                                                                       */
/* 13 Aug 97 S.Belforte: original creation                               */
/* 21 Aug 97 S.Belforte: clean up                                        */
/* 22 Aug 97 S.Belforte: register GODW_0. GODW_1                         */
/* 25 Aug 97 S.Belforte: explicit al cases for full state of fsm, no     */
/*                       else statement                                  */
/* 28 Aug 97 S.Belforte: FACTOR version: factorize out the fsm part, to  */
/*                                       make it common to all glues     */
/*  2 Sep 97 S.Belforte: remove OVERFLOW register                        */
/*                                                                       */
/*************************************************************************/

`timescale 1ns/1ns

module glue2x11 (CLK, RESET,
                   ADDDW_0, ADDDW_1, DVDW_0, DVDW_1, GODW_0, GODW_1,
                   ADDUP, DVUP, GOUP);

parameter INPUT_WIDTH = 11;

  input        CLK;
  input        RESET;
  input        DVDW_0;
  input        DVDW_1;
  input        GOUP;
  output       DVUP;
  output       GODW_0;
  output       GODW_1;
  input [INPUT_WIDTH-1:0] ADDDW_0;
  input [INPUT_WIDTH-1:0] ADDDW_1;
  output[INPUT_WIDTH:0] ADDUP;

  reg   [INPUT_WIDTH:0] ADDUP;
//
// local nets
//
  
  wire  [INPUT_WIDTH:0] ADDDW;
  wire         DVDW;
  wire         SEL;
  wire         SELOVF;
  wire         CE_UP;
  wire         CE_OVF;

//
//-------------------------------------------------
//
//
// priority encoding and multiplexing logic
//
  assign DVDW   =  DVDW_0 || DVDW_1;
  assign SEL    = !DVDW_0 && DVDW_1;
  assign ADDDW  = (SEL==0) ? {1'b0,ADDDW_0} : {1'b1,ADDDW_1} ;
//
// address registers
//
  always @ (posedge CLK)
    begin #1
      if (CE_UP)
	ADDUP = ADDDW;
    end
//
// fsm
//
  oglue_fsm fsm (CLK, RESET, SEL, DVDW, GOUP,
             DVUP, GODW_0, GODW_1, CE_UP);

  endmodule