/*************************************************************************/
/*                GL0_2x10                                               */
/*                                                                       */
/* 2-in 1-out 10-bit GLUE0 for the AMFPGA output glue chip (OGLUE)       */
/* Combines 2 10-bit address bysses from 2 AMFPGA chains into one 11-bit */
/* Interfaces the AMFPGA OR/SEL protocol with the OGLUE DV/GO protocol   */
/* To make this conversion the following identification of up-side       */
/* signals will be usefull:                                              */
/*          BUSY == DVUP  tells higher glue that data are ready          */
/*          FREE == GOUP  higher glue signals that it read current data  */
/* Takes care of the fact (and only works IF !) AMFPGA clock is at least */
/* a factor 2 slower then OGLUE clock                                    */
/* Besides name changes, is almost identical to original Fill_L0buffer   */
/* written by Paola Giannetti, just add RESET signal for async reset     */
/*                                                                       */
/*                                                                       */
/* 13 Aug 97 S.Belforte: original creation                               */
/* 21 Aug 97 S.Belforte: update address on posedge, but SEL on negedge   */
/*                       of clock (introduce READY flag) as from Paola   */
/* 22 Aug 97 S.Belforte: Modify BUSY: once set stays 1 until FREE comes  */
/*                                    regardless of CE going away        */
/*                                                                       */
/*  2 Sep 97 S.Belforte: Synopsis wants one simple signal as reset for   */
/*                       BUSY, introduce BUSY_RESET. Also Synopsis needs */
/*                       delays in assignement lines in begin-end for    */
/*                       BUSY and READY ff, not as separate statements   */
/*  5 Sep 97 S.Belforte: adapt to latest AMfpga specs from Paola: OR     */
/*                       must be registered on clock negedge and only    */
/*                       resulting ORint is to be used in logic          */
/*                                                                       */
/*************************************************************************/

`timescale 1ns/1ns

module gl0_2x10  (CLK, RESET,
                  AMADD, OR_0, OR_1, SEL_0, SEL_1,
                  ADDUP, BUSY, FREE);

  input        CLK;
  input        RESET;
  input        OR_0;
  input        OR_1;
  input        FREE;
  output       BUSY;
  output       SEL_0;
  output       SEL_1;
  input  [9:0] AMADD;
  output[10:0] ADDUP;

  reg   [10:0] ADDUP;
  reg          BUSY;

//
// local nets
//
  reg          READY;
  reg          ORint_0, ORint_1;
  
  wire         SEL;
  wire         CE;
  wire         BUSY_RESET;
//
//-------------------------------------------------
//
// OR_ register
//
  always @ (negedge CLK)
    begin
      ORint_0 = OR_0;
      ORint_1 = OR_1;
    end

// address multiplexing logic
// SEL is 0 if OR_0 is 1, SEL is 1 if OR_1 is 1 but OR_0 is 0.
//
  assign SEL    = !ORint_0 && ORint_1;
//
// priority encoding
//
  assign SEL_0 = ORint_0             && READY;
  assign SEL_1 = ORint_1 && !ORint_0 && READY;
//
// address register clock enable, also sets the BUSY flag
//
  assign CE = (ORint_0 || ORint_1) && READY;
//
// address register
//
  always @ (posedge CLK)
    begin #1
      if (CE) ADDUP = {SEL,AMADD};
    end
//
// BUSY flag register
//
  assign BUSY_RESET = FREE || RESET;
  always @ (posedge CLK or posedge BUSY_RESET)
    begin
      if (BUSY_RESET) #1 BUSY = 0;
      else if (CE) #1 BUSY = 1;
    end
//
// READY flag register
//
  always @ (negedge CLK or posedge RESET)
    begin
      if (RESET) READY = 1;
      else READY = !BUSY;
    end
  endmodule